Many memory systems utilize bit line precharging to facilitate the detection of stored data by an output driver during a read access. Synchronous precharging systems typically use certain clock edges to trigger various events including memory precharging. However, as the address information typically is available before the clock edge, the reliance on the clock edge typically introduces timing bubbles that slow memory access processing. Moreover, detrimental issues related to synchronous precharging, such as skew, jitter and set-up times, can accumulate over multiple clock cycles in these conventional precharging systems, thereby impeding timely access to memory. Accordingly, an improved technique for memory precharging would be advantageous.
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